1. Field of the Invention
The present invention relates to a semiconductor apparatus and a method of manufacturing the same and, more particularly, to construction of a DRAM (Dynamic Random Access Memory) utilizing heat-resistant capacitor cells and a method of manufacturing the DRAM.
2. Description of the Prior Art
In a highly integrated semiconductor device such as, for example, a 256 M-bit DRAM or the like, a high dielectric material such as PZT (titanic acid zircon acid lead) or the like is used for the capacitor dielectric film, in addition to the use of the stacked capacitor construction of a multilayered structure, in an attempt to reduce the size of a capacitor to thereby increase the integration density of elements.
The prior art DRAM is shown in FIG. 21 in a partial sectional view.
Referring to FIG. 21, the major surface of a P-type semiconductor substrate 101 has a field oxide film 102 separated from other elements to leave an activation region on the major surface of the substrate 101 where N-type impurity regions 106a, 106b and 106c which eventually form source-drain regions, are formed. Transfer gate transistors 103a and 103b, each having a gate electrode 104a or 104b formed on a corresponding channel region 121 with a gate insulating film 105 intervening therebetween, are formed between the neighboring members of the impurity regions.
On the other hand, a gate electrode 104d of the other transfer gate transistor extends onto the field oxide film 102, and an oxide film 107 is formed so as to overlay the gate electrodes 104b, 104c and 104d.
An embedded bit wire 108 connected electrically with the impurity region 106a is formed on the impurity region 106a, which wire 108 is in turn covered by an insulating layer 109.
Also, to cover the insulating film 109 and the oxide film 107, a first interlayer insulating film 110 having its top face flattened. A contact hole 110a is defined in a portion of the first interlayer insulating film 110 immediately above the impurity region 106b, and a connecting member (plug) 111 containing Si as a principal component and electrically connected with the impurity region 106b is embedded within the contact hole 110a.
A lower capacitor electrode 130 made of platinum is formed in an electrically connected fashion on an upper surface of the connecting member 111 through a diffusion preventing film 129. Further, a capacitor dielectric film 115 made of PZT, SrTiO.sub.3 or the like, and an upper capacitor electrode 116 made of platinum are deposited one above the other so as to overlay the lower capacitor electrode 114.
Further, a second interlayer insulating film 117 is deposited on an upper capacitor electrode 116 so as to cover the latter and has its top face flattened. First aluminum wiring layers 118 are formed on the flat top surface of the second interlayer insulating film 117 and spaced a distance from each other, and are covered by a protective film 119 which is in turn covered by a second aluminum wiring layer 120.
The prior art DRAM of the structure described above has an advantage in that since the lower capacitor electrode 130 is made of platinum, the lower capacitor electrode 130 does hardly react with the capacitor dielectric film 115 with no reaction layer substantially formed at the interface between the capacitor electrode 130 and the capacitor dielectric film 115. However, because of inferior reactivity and difficulty in machining, difficulty has been encountered in highly integrating the DRAM which requires a microfabricating technique.
Also, to prevent Si in the connecting member 111 from being diffused within the platinum electrode, the diffusion preventing film 129 has been necessitated beneath the platinum electrode 130.
On the other hand, it has been suggested to use an easily workable ruthenium or iridium as material for the lower capacitor electrode 130, but the use of ruthenium or iridium would bring about the following problems because of higher reactivity than that of the platinum.
Namely, ruthenium or the like had a first problem in that silicide tends to be formed through reaction with Si in the connecting member (plug) 111 provided in the lower portion of the lower capacitor electrode 130, accompanied by deformation in shape of the lower capacitor electrode 130 to such an extent as to result in increase the capacitor leak current, when it is exposed to a high temperature during a heat treatment such as annealing employed to flatten the interlayer insulating film.
Also, when ruthenium or iridium is used for the lower capacitor electrode 130 and/or the capacitor upper electrode 116, there is a second problem in that separation may take place between the electrode and the interlayer insulating film due to inferior bondability with the interlayer insulating film to thereby reduce the manufacturing yield of the DRAMs. On the other hand, mere provision of a bond layer between the lower capacitor electrode and the interlayer insulating film may result in deformation in shape of the lower capacitor electrode as a result of stress set-up occurring between the bond layer and the lower capacitor electrode, accompanied by reduction in capacitor characteristic.
In the manufacture of the DRAM, a heat treatment is carried out after formation of the lower capacitor electrode 130 for the purpose of improving the crystalline property of the capacitor dielectric film 115 and also to improve the contact between the metallic wiring and the connecting member 111. During such heat treatment, ruthenium or the like used for the lower capacitor electrode 130 tends to be oxidized resulting in not only surface irregularities, but also deformation in shape of the lower capacitor electrode 130, to such an extent as to increase the capacitor leak current.